STA Interview Questions

oDefining Modes: Different operating modes are : Functional mode - FUNC and test Modes: Scan Shift, Scan Capture, BIST

• Defined in MCMM setup with create_constraint_mode command and given separate SDC of each mode.
• Separate SDC Files: Each SDC file contains the appropriate set_case_analysis settings, relevant clock definitions (test clocks might differ from functional clocks), and potentially different timing exceptions or I/O delays specific to that mode.
• Mode-Specific Constraints within one SDC: Less commonly, complex logic within a single SDC file might be used to apply constraints conditionally, but separate SDCs or set_case_analysis are standard.

Checking Simultaneously (MMMC):

o We need to reduce cell delay or Net delay or use more skew – can use various methods for each.

• o Reduce Cell Delay:

• oCell Sizing (Upsizing): Increase drive strength of cells on the critical path. (Effective for small to moderate violations).

• oVT Swapping (Lowering Vt): Swap cells to faster, lower-Vt variants (HVT->SVT->LVT). (Effective, but increases leakage).

• oReduce amount of buffering if excessive bufs are added.

• o Reduce Net Delay:

oPath Summary:

Startpoint: Where the path begins (input port or flop clock pin).

Endpoint: Where the path ends (output port or flop data input pin).

Path Group:

Path Type: Setup, Hold, Recovery, Removal, Min Pulse Width, etc.

Slack:

Data Arrival Time Path: Details the delay contribution of each element along the data path:

Clock Network Delay (Launch): Latency from clock source to launch flop clock pin (relevant post-CTS).

Clock-to-Q Delay: Delay through the launch flop.

oNO. Even if setup and hold timing checks pass, significant Design Rule Violations (DRVs) either on data or clock needs to be fixed.

Reliability: Slow transitions (max_transition violation) make sequential elements susceptible to noise, glitches, and potential metastability

Timing Accuracy: buffers/inverters are characterized based on expected input transitions and output loads. Violating max_transition or max_capacitance means the library timing models used for setup/hold analysis are inaccurate, invalidating the “clean” timing result. The actual delays might be worse.

oIf setup and hold both are critical on same path, check if it is exact same path or if there is any diversion from combo logic in setup and hold timing path.

If there is any diversion, add delay at that point so hold can be fixed without touching setup critical path.

• If timing path is exactly same and having setup and hold violations, there could be two reasons,
• Crosstalk impact – crosstalk will add delay in setup and reduce it in hold. Impacting adversely both setup and hold. Fixing crosstalk should give margin to fix setup and hold.
• If there is no crosstalk, there can be very high setup and hold time requirement from endpoint. (may happen with reg2mem paths)
• Check if such cells can be replaced with less access time cell.
• To get margin in setup and hold both, you need to use cell with less delay variation across SS-FF corners.
• Use LVT cells in data path instead of SVT/HVT. Use low drive strength cells and reduce net legth so that OCV impact can be reduced giving margin for setup and hold.

o Register-to-Register (Reg2Reg): Starts at the clock pin of a launch flip-flop/latch and ends at the data input pin (e.g., D) of a capture flip-flop/latch. Both launch and capture elements are controlled by related clocks (often the same clock). This is the most common type of path analyzed for setup/hold within a synchronous design.

Input-to-Register (In2Reg): Starts at a primary input port of the design and ends at the data input pin of a sequential element. Constrained by set_input_delay.