Routing Interview Questions

o **Routing (**routeDesign or similar): This stage focuses on physically connecting the pins of all standard cells and macros. goal is connectivity and DRC correctness.

Sub-stages: Often involves Global Routing (planning paths through routing regions/GCells), Track Assignment (assigning nets to specific tracks), and Detail Routing (drawing the exact wires and vias, ensuring DRC rules like spacing/width are met).

Timing/Optimization: Basic timing considerations might influence routing choices (e.g., prioritizing critical nets), but large-scale timing optimization (like cell sizing, buffer insertion) is not the primary focus. The main goal is to achieve a DRC-clean, fully routed design.

oMismatch with Layout: An outdated SPEF reflects an older version of the layout. If placement or routing has changed since the SPEF was generated, the RC values in the SPEF will not accurately represent the current physical structure. Wire lengths, adjacencies (coupling capacitance), and via counts will be wrong.

• Mismatch with Process/Library: If the RC corner data itself is outdated (e.g., from a previous PDK version or library characterization), the fundamental R-per-square or C-per-unit-length values used for extraction might be incorrect for the current process target, even if the layout is current.

For ex, if earlier net was longer and hence in old spef, RC is more. Now latest db, net is short, RC is less but using old spef hence timing calculation will be pessimistic and vice versa.

o Increased Wire Length (Detouring): Due to congestion or blockages, detailed router can detour nets. eGR doesn’t detour to report max congestion. This results in difference in earlied net length estimation causing more RC delay and cell delay if more bufs added.

Accurate Parasitic Extraction (RC Extraction): eGR may use tQrc which is fast but less accurate. Detail routing mostly uses iQrc or QRC for extraction which is more accurate resulting in timing degradation.

o NDRs Used: The most common NDR applied was Double Width, Double Spacing (2W2S) for the main trunk and branch lines of the clock tree. For very critical top-level clock spines, sometimes Triple Width (3W) or wider rules were considered, depending on EM requirements and foundry recommendations.

Using 2W2S Till Leaf Cells:

Generally NO. not necessary and highly undesirable.

Congestion: number of leaf-level clock nets is enormous. Applying 2W2S universally would consume excessive routing resources, especially on lower layers where usually pin connections occur