Routing Interview Questions

We can analyse Congestion hotspot at different stage:

• eGR hotspot at preCTS or post-CTS opt - the step just before routing
• NR-GR hotspot before detail routing

After detail routing we check for DRCs and Shorts.

Congestion Maps: Similar to placement congestion analysis, PnR tools generate visual congestion maps based on eGR or NR-GR

Overflow Reports: Tools provide reports listing GCells with overflow (demand > supply) and quantifying the overflow percentage or the number of overflowing tracks. This helps pinpoint the most problematic areas.

oWe can run IR aware full flow

• IR aware placement : Spread high power density hotspots to reduce IR drop. Tools settings using setPlaceMode. This is useful even during routing as during optimization tool adds buf/inv and updates placement increamentally.
• CCopt/SkewClock: skew the clock to minimize peak current
• Reinforce_pg: Auto RPG: Loacl PG stripe/via addition in hotspot area. (separate utility from cadence. Needs voltus IR setup as input.
• Fill: Maximize PG hookup at signoff stage.
• https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009foP9EAI&pageName=ArticleContent

In general routers are now performs rudimentary current density estimation on wires and handles IR/RM.

Congestion reported by eGR fafter place or CTS is more as, eGR detours less to avoid congestion, it helps finding congestion before hand instead of detouring nets. Fixing congestion after route is usually difficult and it should be addressed by placement stage.

Route Effort: Increase the effort level of the detailed router (setRouteMode -detEffort high). The tool will spend more time trying alternative paths or rip-up and reroute techniques.

Congestion-Driven Routing:

The net with double width will generally have less delay.

Reasoning (RC Delay): Wire delay is primarily determined by the product of its resistance (R) and capacitance (C).

Resistance (R): Resistance is inversely proportional to the cross-sectional area of the wire. For a fixed thickness (T), resistance is inversely proportional to width (W). R ∝ 1 / (W * T). Doubling the width (W -> 2W) approximately halves the resistance (R -> R/2).

o Netlist vs. Layout: LVS clean. If design has shorts, it results in inaccurate extraction for those nets. So LVS clean is preferred.

SPEF File Validity: Check if any issues or critical warning in extraction flow. If there are ignored nets during extraction, paths with those nets will not have accurate timing.

Other consistency chek like Lib and SDC, no missing constraints.

Annotation Check (report_annotated_delay/check): After reading SPEF/SDF, verify that parasitic delays and checks have been successfully annotated onto the design nets and cells. Look for warnings about unannotated elements.

o Via Pillar: A structure used in advanced process nodes (like FinFET nodes) to create a lower-resistance vertical connection between metal layers compared to traditional single vias or via arrays. It typically consists of:

Stacked, short metal segments (“fingers”) on intermediate metal layers, aligned vertically.

These segments are connected by vias above and below, essentially forming a “pillar” of alternating via and short metal bar segments running vertically through multiple layers.