Pre-PnR Interview Questions

oReg2Reg WNS/TNS:

Acceptable: A small negative WNS (e.g., -50ps to -200ps for a multi-GHz design, perhaps -10% to -20% of the clock period) might be considered acceptable as a starting point for PnR. TNS should ideally be manageable.

Context: The acceptable value depends on how much improvement is expected from PnR optimizations (better placement, buffering, useful skew, more accurate parasitics).

• Extremely High Negative WNS/TNS: If the WNS is very large negative (e.g., approaching or exceeding the clock period) or TNS is enormous:

Unrealistic Constraints: Clock frequency target is too high for the technology/architecture. SDC constraints (I/O delays, exceptions) might be incorrect or too tight.

• oNetlist Checks:

o Syntactic Correctness: Ensure the Verilog netlist format is correct and parsable by the PnR tool.

o Logical Equivalence Check (LEC): Formally verify that the synthesized netlist is logically equivalent to the golden RTL

o Connectivity Issues:

§ Floating Inputs: No gate input pins should be left unconnected (floating)

§ Multi-Driven Nets: Check for nets driven by more than one output

§ Unloaded Nets/Outputs: Outputs driving no load might indicate redundant logic or connectivity errors.