Pre-PnR Interview Questions

Check_timing : It looks for issues in the design and constraint setup, such as

• Unconstrained endpoints

• Combinational feedback loops

• Empty or unclocked registers

• Generated clocks with no source

• Timing exceptions

(false/multicycle paths) without valid paths

Report_timing: Used to check various timing reports like, setup, hold, etc…

Scripting: Tcl scripts can be written to trace paths between registers (e.g., using all_fanin/all_fanout recursively or dedicated path tracing commands) and count the number of combinational cells encountered.

oClean Sanity Checks: The netlist must pass all critical sanity checks:

No fatal errors in check_design / check_netlist (no multi-driven nets, no floating inputs on critical paths, correct connectivity).

No unresolved references (check_library passes, all cells have lib/lef).

No critical errors in check_timing (all clocks defined, critical paths constrained, no unconstrained registers intended to be clocked). Minor unconstrained paths might be acceptable if understood and deemed non-critical or intended false paths.

Configure the tool to find the required library files (.lib, .lef).

• Innovus:
• ICC2: set_app_var search_path ./libs ; set_app_var target_library {slow.db} ; set_app_var link_library “* slow.db” (Specify LEF via read_tech_lef, read_cell_lef or read_ndm)
• Load Physical Libraries (.lef**):** Read the technology LEF and the standard cell/macro LEF files.

Innovus: Handled by init_design if paths are set, or read_lef tech.lef cells.lef

ICC2: read_tech_lef tech.lef ; read_cell_lef cells.lef (or read_ndm for NDM libraries which bundle lib/lef)

• Gate-Level Netlist:
• Timing Libraries (.lib or .db**)**
• Physical Libraries (.lef**):**
• technology process rules (tech LEF).
• Timing Constraints (SDC - Synopsys Design Constraints):
• Power Intent (UPF/CPF - Optional but common):
• RC Extraction Files (Optional initial estimate, more critical later): tlu+, qrcTech
• Floorplan Definition File (DEF - Optional):
• Scan Definition File (Scan DEF - Optional):
• MMMC (Multi-Mode Multi-Corner) Setup File

oSDC Version: Specifies the SDC standard version used (e.g., set sdc_version 2.1).

Units: Defines units for time, capacitance, resistance, voltage, current, power (e.g., set_units -time ns …).

Clock Definitions:

create_clock: Defines primary clocks entering the design (at ports or internal pins), specifying their source, period, waveform (duty cycle, edge times).

create_generated_clock: Defines clocks generated internally (e.g., by PLLs, clock dividers/multipliers) based on a master clock.

set_clock_groups: Defines relationships between clocks (synchronous, asynchronous, exclusive).