Pre-PnR Interview Questions

oClean Sanity Checks: The netlist must pass all critical sanity checks:

No fatal errors in check_design / check_netlist (no multi-driven nets, no floating inputs on critical paths, correct connectivity).

No unresolved references (check_library passes, all cells have lib/lef).

No critical errors in check_timing (all clocks defined, critical paths constrained, no unconstrained registers intended to be clocked). Minor unconstrained paths might be acceptable if understood and deemed non-critical or intended false paths.

Configure the tool to find the required library files (.lib, .lef).

• Innovus:
• ICC2: set_app_var search_path ./libs ; set_app_var target_library {slow.db} ; set_app_var link_library “* slow.db” (Specify LEF via read_tech_lef, read_cell_lef or read_ndm)
• Load Physical Libraries (.lef**):** Read the technology LEF and the standard cell/macro LEF files.

Innovus: Handled by init_design if paths are set, or read_lef tech.lef cells.lef

ICC2: read_tech_lef tech.lef ; read_cell_lef cells.lef (or read_ndm for NDM libraries which bundle lib/lef)

oSDC Version: Specifies the SDC standard version used (e.g., set sdc_version 2.1).

Units: Defines units for time, capacitance, resistance, voltage, current, power (e.g., set_units -time ns …).

Clock Definitions:

create_clock: Defines primary clocks entering the design (at ports or internal pins), specifying their source, period, waveform (duty cycle, edge times).

create_generated_clock: Defines clocks generated internally (e.g., by PLLs, clock dividers/multipliers) based on a master clock.

set_clock_groups: Defines relationships between clocks (synchronous, asynchronous, exclusive).

oReg2Reg WNS/TNS:

Acceptable: A small negative WNS (e.g., -50ps to -200ps for a multi-GHz design, perhaps -10% to -20% of the clock period) might be considered acceptable as a starting point for PnR. TNS should ideally be manageable.

Context: The acceptable value depends on how much improvement is expected from PnR optimizations (better placement, buffering, useful skew, more accurate parasitics).

• Extremely High Negative WNS/TNS: If the WNS is very large negative (e.g., approaching or exceeding the clock period) or TNS is enormous:

Unrealistic Constraints: Clock frequency target is too high for the technology/architecture. SDC constraints (I/O delays, exceptions) might be incorrect or too tight.

• oNetlist Checks:

o Syntactic Correctness: Ensure the Verilog netlist format is correct and parsable by the PnR tool.

o Logical Equivalence Check (LEC): Formally verify that the synthesized netlist is logically equivalent to the golden RTL

o Connectivity Issues:

§ Floating Inputs: No gate input pins should be left unconnected (floating)

§ Multi-Driven Nets: Check for nets driven by more than one output

§ Unloaded Nets/Outputs: Outputs driving no load might indicate redundant logic or connectivity errors.