Power-Plan Interview Questions

Based on, on which layer macros has pins, we can drop via on top of that layer or do direct connection on pin layer. Different macros may have different internal structure and hence pins at different layers.

oIncreased Resistance: Interconnect wires become thinner and taller (to try and mitigate R increase, but R still dominates over C). Via resistance also increases dramatically. This makes the power grid inherently more resistive, leading to higher IR drop (V=I×R).

• Lower Supply Voltage (Vdd): Operating voltages are significantly lower (e.g., < 0.8V). This means the allowable noise margin for IR drop (both static and dynamic) is much smaller (e.g., 5-10% of Vdd is a smaller absolute voltage). Designs become extremely sensitive to voltage variations.
• Higher Current Density: While voltage decreases, the density of transistors increases significantly, leading to higher overall current density (J) in the power grid, especially localized hotspots. Risk of EM.
• Dynamic IR Drop (Voltage Droop): Faster switching speeds and higher localized current demands exacerbate dynamic voltage droop. Providing sufficient instantaneous current through the high-resistance grid requires a very dense decap cell strategy and a robust PDN.
• Complexity of PDN Design: Achieving the required low resistance and meeting IR/EM targets often necessitates using more metal layers for the power grid, wider straps, and significantly more vias, consuming valuable routing resources needed for signals. Balancing power needs with signal routability becomes harder.

7nm Challenges (includes power/interconnect): https://www.wipro.com/blogs/mohit-bansal/the-benefits-and-challenges-of-7nm-technology/

oHeader Switches: Use PMOS transistors placed between the main VDD grid (always-on supply) and the switchable VDD rail of the power domain (VDD_SW). The PMOS gate is controlled by the sleep/enable signal. When OFF (sleep signal asserted), they disconnect the domain from VDD.

• Footer Switches: Use NMOS transistors placed between the switchable VSS rail (VSS_SW) of the power domain and the main VSS grid (always-on ground). The NMOS gate is controlled by the sleep/enable signal. When OFF, they disconnect the domain from VSS.
• Combined Header/Footer: Some designs might use both header and footer switches for more robust power cut-off, although this adds complexity and area.

oVoltage islands (or power domains operating at different voltage levels) are created primarily to reduce overall power consumption (both dynamic and static).

Dynamic Power Reduction: Pdynamic​∝Vdd2​. By operating non-performance-critical blocks (islands) at a lower supply voltage (e.g., 0.7V) compared to performance-critical blocks (e.g., 0.9V), the dynamic power consumption of the low-voltage blocks is significantly reduced.

Static Power Reduction: Pstatic​∝Vdd​×Ileakage​. Lowering Vdd directly reduces static power. Additionally, leakage current (Ileakage​) itself often decreases at lower voltages.

• Primary Purpose: To prevent signal corruption from propagating from an inactive domain to an active domain.
• Isolation & Level Shifters: https://vlsitutorials.com/isolation-cells-level-shifter-cells-low-power-vlsi/