Power-Plan Interview Questions

o Via Pillar: A structure used in advanced process nodes (like FinFET nodes) to create a lower-resistance vertical connection between metal layers compared to traditional single vias or via arrays. It typically consists of:

Stacked, short metal segments (“fingers”) on intermediate metal layers, aligned vertically.

These segments are connected by vias above and below, essentially forming a “pillar” of alternating via and short metal bar segments running vertically through multiple layers.

o Static Power: Power consumed when the circuit is powered ON but not actively switching. It’s primarily due to leakage currents flowing through transistors that are supposed to be OFF.

Main Components: Subthreshold leakage, gate leakage, junction leakage.

Factors: Increases significantly with lower threshold voltages (Vt) and at smaller technology nodes. Also increases with temperature.

Dynamic Power: Power consumed during the switching of logic states (when signals transition between ‘0’ and ‘1’).

Cell Sizing / (Downsizing): Replace cells on non-critical timing paths with smaller drive-strength variants (e.g., X4 -> X2 -> X1).

Removing unnecessary buf/inverters: If added on short nets, may not be really required and can be deleted.

Leakage Optimization Modes: PnR/Optimization tools often have specific modes or commands (setOptMode -powerEffort high, optimize_power)

Clock Gating Enhancement: While primarily done during synthesis/CTS, post-route optimization might identify further opportunities for clock gating refinements or sizing of clock gating cells themselves, assuming it doesn’t impact timing.

o Creating a Voltage Area (Physical Implementation): A voltage area is a physical region on the chip floorplan designated to contain logic operating at a specific voltage level different from other regions, or logic that can be power-gated:

Define the physical boundary (coordinates) of the region- create_voltage_area

Associate this region with a specific power domain defined in the UPF/CPF.

cells belonging to the corresponding power domain are placed within this physical voltage area during placement.

oRequirement Analysis: Understand the power consumption estimate of the design (static and dynamic), voltage levels required, number of power domains, IR drop targets, and EM limits.

• Define Structure: Design the hierarchy of the PDN, typically involving:
• Power Pads/Bumps
• Power Rings
• Power Stripes:
• Power Rails

Calculate Widths/Spacing: Determine the required width and spacing of rings and stripes based on current density requirements

Layer Assignment: Assign specific metal layers for rings, horizontal stripes, and vertical stripes.

• Logical Grouping (UPF create_power_domain -elements**):** All instances specified as elements of a power domain ideally need to be placed together physically.
• Area Estimation: Estimate the total area required for all the standard cells and macros belonging to the power domain. Add margin for internal routing, CTS buffers, and special cells (power switches, isolation cells often placed at the boundary).
• Power Grid Considerations: The voltage area needs its own internal power grid distribution (stripes/rails) connected appropriately to either the global grid (for always-on domains) or through power switches (for switchable domains). The size and shape must accommodate this grid.
• Based on above factors and required utilization of voltage area, we can determine domain area.
• The voltage area (create_voltage_area): Associate the physical area with the logical power domain name from UPF. Use placement guidance features (regions, fences) to enforce that cells belonging to the domain are placed within the defined voltage area.