Power-Plan Interview Questions

o Via Pillar: A structure used in advanced process nodes (like FinFET nodes) to create a lower-resistance vertical connection between metal layers compared to traditional single vias or via arrays. It typically consists of:

Stacked, short metal segments (“fingers”) on intermediate metal layers, aligned vertically.

These segments are connected by vias above and below, essentially forming a “pillar” of alternating via and short metal bar segments running vertically through multiple layers.

o Static Power: Power consumed when the circuit is powered ON but not actively switching. It’s primarily due to leakage currents flowing through transistors that are supposed to be OFF.

Main Components: Subthreshold leakage, gate leakage, junction leakage.

Factors: Increases significantly with lower threshold voltages (Vt) and at smaller technology nodes. Also increases with temperature.

Dynamic Power: Power consumed during the switching of logic states (when signals transition between ‘0’ and ‘1’).

o Creating a Voltage Area (Physical Implementation): A voltage area is a physical region on the chip floorplan designated to contain logic operating at a specific voltage level different from other regions, or logic that can be power-gated:

Define the physical boundary (coordinates) of the region- create_voltage_area

Associate this region with a specific power domain defined in the UPF/CPF.

cells belonging to the corresponding power domain are placed within this physical voltage area during placement.

oIncreased Resistance: Interconnect wires become thinner and taller (to try and mitigate R increase, but R still dominates over C). Via resistance also increases dramatically. This makes the power grid inherently more resistive, leading to higher IR drop (V=I×R).

• Lower Supply Voltage (Vdd): Operating voltages are significantly lower (e.g., < 0.8V). This means the allowable noise margin for IR drop (both static and dynamic) is much smaller (e.g., 5-10% of Vdd is a smaller absolute voltage). Designs become extremely sensitive to voltage variations.
• Higher Current Density: While voltage decreases, the density of transistors increases significantly, leading to higher overall current density (J) in the power grid, especially localized hotspots. Risk of EM.
• Dynamic IR Drop (Voltage Droop): Faster switching speeds and higher localized current demands exacerbate dynamic voltage droop. Providing sufficient instantaneous current through the high-resistance grid requires a very dense decap cell strategy and a robust PDN.
• Complexity of PDN Design: Achieving the required low resistance and meeting IR/EM targets often necessitates using more metal layers for the power grid, wider straps, and significantly more vias, consuming valuable routing resources needed for signals. Balancing power needs with signal routability becomes harder.

7nm Challenges (includes power/interconnect): https://www.wipro.com/blogs/mohit-bansal/the-benefits-and-challenges-of-7nm-technology/

oVoltage islands (or power domains operating at different voltage levels) are created primarily to reduce overall power consumption (both dynamic and static).

Dynamic Power Reduction: Pdynamic​∝Vdd2​. By operating non-performance-critical blocks (islands) at a lower supply voltage (e.g., 0.7V) compared to performance-critical blocks (e.g., 0.9V), the dynamic power consumption of the low-voltage blocks is significantly reduced.

Static Power Reduction: Pstatic​∝Vdd​×Ileakage​. Lowering Vdd directly reduces static power. Additionally, leakage current (Ileakage​) itself often decreases at lower voltages.