Placement Interview Questions

o Identify the Bottleneck: Determine why the hotspot exists even with uniform density targets. Is it due to:

Macro pin congestion?

A narrow channel between macros/blockages?

A concentration of high-pin-count cells?

Specific routing patterns forced by the logic structure?

• partial placement blockages or density screens specifically over the hotspot GCells. This forces lower density only where needed, rather than globally.
• Macro/Blockage Adjustments:

Cell Padding: Apply cell padding specifically to cells within the congested region, or to specific cell types causing the issue there.

Use area aware synthesis and placement.

Place macros carefully to give maximum std cell placeable area. Use congestion driven placement to reduce high utilization impact on congestion.

oEnsure that partial blockages are not too restrictive. If a region is 50% blocked, and nearby area is full, cells may crowd into corners.

• Create blockage in distributed area. https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009mFGeEAM&pageName=ArticleContent
• If found that one particular module or instances that can be identified in patterns, is crowded at corner, give cell padding.

oBuffers/inverters for optimization

• Physical only cells added like decap, endcaps, well taps etc.
• CTS structure adds buff/inv.
• Blockages/halos added in floorplan.
• Scan chain reordering, normal FF to scan FF increases area. Hold fix in Scan modes

oPlacement Legality: check for Overlaps: Verify that no standard cells overlap each other (checkPlace, checkLegality). All cells must occupy legal sites defined by the floorplan rows.

Congestion Analysis:

Global Congestion Map:

Density Checks:

Timing Analysis (Pre-CTS):

Setup Timing: the violations should be reasonable and manageable for subsequent optimization stages. Acceptable violation depends on what kind of cells used, whether LVT enabled or not at place, what is extra uncertainty given etc.

o Inaccurate Wire Load Models (WLMs) in Synthesis: Synthesis often uses statistical WLMs to estimate interconnect delay, which can be highly inaccurate compared to the actual delays based on physical placement.

Large Distance: Macros or blocks that communicate frequently are placed too far apart, leading to long interconnect delays.

Congestion: High placement congestion forces routing detours (even in trial route estimates), increasing wire length and delay.

Bad Pin Placement

Placement Density: Placing cells too densely, even if not causing severe congestion, results in longer average wire lengths compared to a sparser placement.