Placement Interview Questions

oplaceDesign / place_opt

• setPlaceMode -cell_padding <value>
• set_cell_padding -lib_cells <lib_cell_list> -right <value> -left <value>

Cell Sizing / (Downsizing): Replace cells on non-critical timing paths with smaller drive-strength variants (e.g., X4 -> X2 -> X1).

Removing unnecessary buf/inverters: If added on short nets, may not be really required and can be deleted.

Leakage Optimization Modes: PnR/Optimization tools often have specific modes or commands (setOptMode -powerEffort high, optimize_power)

Clock Gating Enhancement: While primarily done during synthesis/CTS, post-route optimization might identify further opportunities for clock gating refinements or sizing of clock gating cells themselves, assuming it doesn’t impact timing.

Cell Sizing, VT Swap to allowed VT at placement, Buffer insertion, Logic optimization, These optimizations are typically performed automatically by the place_opt / optDesign -preCTS commands based on the timing constraints (SDC) and available libraries and don’t use settings.

• Need manual observation of critical paths,
• high fanout: it can cause trouble in closing timing as balancing CTS and placing all FFs properly will be difficult for the tool.
• Cells are spread for longer distance: check the connectivity of start point endpoint, analyse module connection and give appropriate bound or region.
• Macro placement analysis and fanin fanout checks gives better idea.

oCongestion Maps: Use the PnR tool’s GUI to visualize the congestion map generated after trial/global routing. Identify hotspots (high overflow areas, usually color-coded red/orange). Check both horizontal and vertical layer congestion.

• reportCongestion - list the most congested regions.

Reasons could be - High Cell Density - Macro Pin Areas - Narrow Channels - Bad Floorplan - Specific Logic: Are certain types of logic (e.g., large muxes, data path logic) concentrating connections in one area?

oUsually iterative to find best value for padding but can be generalise like,

• If local congestion in one module, depending on congestion %, we can increase.
• If cells has high pin density, padding required might be more.

If height is more, block has longer vertical tracks but less in number. Block has more number of horizontal tracks available. Chances are there will be higher congestion on vertical tracks. So place pins and macros such that it utilises more number of horizontal tracks.