Physical-Verification Interview Questions

o DRC (Design Rule Check): checks if the physical layout is as per foundry rules, ensure it can be manufactured reliably with acceptable yield.

Types of Rules: Include minimum width, minimum spacing (intra-layer and inter-layer), minimum area, via enclosure, overlap requirements, antenna rules (often checked separately but fundamentally DRCs), density rules, and many complex conditional rules (e.g., end-of-line spacing, notch spacing).

Fixing DRCs:

Spacing Violations: Increase the space between the violating shapes (e.g., move wires further apart).

oLVS (Layout Versus Schematic): A critical physical verification process that compares the electrical circuit extracted from the physical layout database (e.g., GDSII, OASIS) against the intended circuit described by the source schematic netlist (e.g., SPICE or Verilog netlist).

• Inputs:
• Layout Database: The physical layout design file (GDSII, OASIS)
• Source Netlist: The “golden” netlist representing the intended circuit schematic (e.g., SPICE netlist for custom designs, Verilog netlist for digital designs).
• Rule Deck: Provided by the foundry, this file tells the LVS tool how to identify devices (transistors, resistors, capacitors, diodes) from the layout layers, how to determine connectivity, and how to extract parameters (like W/L for transistors).
• Configuration/Setup Files: Files to control the LVS run, specify top cells, map power/ground names, define device properties to compare, set tolerances, etc.
• Schematic View vs. Layout View (in LVS context):

Schematic View: Circuit from Golden netlist.

oNetlist used for LVS is PG netlist, meaning it has all PG related components, physical only cells etc. Netlist used for PT has cells required for functionality.