Physical-Verification Interview Questions

oIncorrect Nets / Connectivity Errors: This section details discrepancies in how nets are connected.

Shorts: When Schematic has more nets but layout has less nets, layout has short.

Opens: A single net in the schematic corresponds to two or more unconnected nets in the layout.

Incorrect Instances / Devices: Discrepancies in the number or type of devices.

Missing Devices: A device present in the schematic is not found in the corresponding location/netlist in the layout.

oLEC (Logical Equivalence Check): Compares Golden netlist or RTL with netlist at any given point in PnR flow to check functionality is same or not.

• Tools like Synopsys Formality or Cadence Conformal are used.
• Non-Equivalent Point: A point (typically a primary output port or a sequential element input/output) in the two designs being compared where the LEC tool has determined that the logic functions driving that point are not equivalent. This indicates a functional difference between the “golden” reference design and the revised/implemented design, meaning the optimization or synthesis process has introduced a functional bug.
• Equivalence Checking Overview: https://www.synopsys.com/glossary/what-is-equivalence-checking.html
• LEC Steps: https://semiconductorclub.com/logic-equivalence-check/

oHigh Leakage from Antenna Cells: Antenna cells typically contain protection diodes connected to the input pins. These diodes, even when reverse-biased during normal operation, contribute a small amount of junction leakage current. If many antenna cells are added throughout the design, this cumulative leakage can become significant, especially in low-power designs.

• Use jogging to upper layer: If resources available, can be routed to upper layer to reduce antenna effect on lower layer. Routing on upper layer may or may not cause new antenna violations depending on what is cumulative metal area of upper layer.
• Floating Cell Addition for Antenna Fixing? Adding a floating cell, with input connected to gate with antenna violation and output floating can help in antenna violation by increasing gate area.
• This can increase the load on the net and may impact the timing.

oDRC (Design Rule Check): Verifies that the layout geometry adheres to the manufacturing constraints (design rules) specified by the foundry for the target technology node. This includes checks for minimum width, spacing, area, enclosure, overlap, etc., for all layers (metal, poly, diffusion, vias, etc.). Ensures the layout can be physically manufactured with acceptable yield.

LVS (Layout Versus Schematic): Compares GDS(Layout) vs schematic(Netlist). It verifies that the layout correctly implements the intended logic in netlist. It checks, device types, and device parameters (like transistor W/L). Checks for shorts, opens, incorrect connections, missing/extra devices, and parameter mismatches.

oIn terms ofSTA:

• When in timing path, there is output of combo logic is used as input in same timing path, it forms, loop causing instability and difficulty in modelling timing for that path.
• https://www.intel.com/content/www/us/en/docs/programmable/683323/18-1/avoid-combinational-loops.html
• In terms of DRC: when layer has DPT enabled and layout is forming a loop in such a way that it is not possible to assign mask1/2 to shapes without causing spacing violations.
• https://semiengineering.com/cut-cut-double-patterning-question/
• https://semiwiki.com/eda/1962-fixing-double-patterning-errors-at-20nm/#:~:text=Move%20single%20edges%20as%20opposed,which%20make%20the%20design%20uncolorable.

o Antenna Effect (Plasma-Induced Gate Oxide Damage): During semiconductor manufacturing, plasma etching processes are used to remove material. In these processes, charged particles (ions, electrons) bombard the wafer surface. If a long metal wire (acting like an “antenna”) connected only to a transistor gate is exposed during etching, it can accumulate significant charge from the plasma. If this charge builds up enough voltage, it can exceed the breakdown voltage of the thin gate oxide layer beneath the transistor gate, causing damage (latent defects or immediate breakdown). This damage can lead to reliability issues or functional failure. The risk increases with the Increase in metal area compared to gate area. Which is called antenna ration.