Physical-Verification Interview Questions

oIncorrect Nets / Connectivity Errors: This section details discrepancies in how nets are connected.

Shorts: When Schematic has more nets but layout has less nets, layout has short.

Opens: A single net in the schematic corresponds to two or more unconnected nets in the layout.

Incorrect Instances / Devices: Discrepancies in the number or type of devices.

Missing Devices: A device present in the schematic is not found in the corresponding location/netlist in the layout.

oDRC (Design Rule Check): Verifies that the layout geometry adheres to the manufacturing constraints (design rules) specified by the foundry for the target technology node. This includes checks for minimum width, spacing, area, enclosure, overlap, etc., for all layers (metal, poly, diffusion, vias, etc.). Ensures the layout can be physically manufactured with acceptable yield.

LVS (Layout Versus Schematic): Compares GDS(Layout) vs schematic(Netlist). It verifies that the layout correctly implements the intended logic in netlist. It checks, device types, and device parameters (like transistor W/L). Checks for shorts, opens, incorrect connections, missing/extra devices, and parameter mismatches.

o Antenna Effect (Plasma-Induced Gate Oxide Damage): During semiconductor manufacturing, plasma etching processes are used to remove material. In these processes, charged particles (ions, electrons) bombard the wafer surface. If a long metal wire (acting like an “antenna”) connected only to a transistor gate is exposed during etching, it can accumulate significant charge from the plasma. If this charge builds up enough voltage, it can exceed the breakdown voltage of the thin gate oxide layer beneath the transistor gate, causing damage (latent defects or immediate breakdown). This damage can lead to reliability issues or functional failure. The risk increases with the Increase in metal area compared to gate area. Which is called antenna ration.

o DRC (Design Rule Check): checks if the physical layout is as per foundry rules, ensure it can be manufactured reliably with acceptable yield.

Types of Rules: Include minimum width, minimum spacing (intra-layer and inter-layer), minimum area, via enclosure, overlap requirements, antenna rules (often checked separately but fundamentally DRCs), density rules, and many complex conditional rules (e.g., end-of-line spacing, notch spacing).

Fixing DRCs:

Spacing Violations: Increase the space between the violating shapes (e.g., move wires further apart).

oLVS (Layout Versus Schematic): A critical physical verification process that compares the electrical circuit extracted from the physical layout database (e.g., GDSII, OASIS) against the intended circuit described by the source schematic netlist (e.g., SPICE or Verilog netlist).

• Inputs:
• Layout Database: The physical layout design file (GDSII, OASIS)
• Source Netlist: The “golden” netlist representing the intended circuit schematic (e.g., SPICE netlist for custom designs, Verilog netlist for digital designs).
• Rule Deck: Provided by the foundry, this file tells the LVS tool how to identify devices (transistors, resistors, capacitors, diodes) from the layout layers, how to determine connectivity, and how to extract parameters (like W/L for transistors).
• Configuration/Setup Files: Files to control the LVS run, specify top cells, map power/ground names, define device properties to compare, set tolerances, etc.
• Schematic View vs. Layout View (in LVS context):

Schematic View: Circuit from Golden netlist.