o Technology LEF (tech.lef): Defines the process technology rules and properties. It contains information common to the entire chip manufacturing process, independent of specific standard cells.
Content:
Layers: Defines all routing (metal), cut (via), masterslice (poly, diffusion), and other layers used in the technology. Includes name, type, direction preference, pitch, width, spacing rules (DRCs), resistance, capacitance per unit area/length, thickness, color (for multi-patterning).
Vias: Defines standard via types connecting different layers, including their cut patterns, enclosure rules, and resistance.
