General-Concepts Interview Questions

What is the difference between std. cell LEF and tech LEF? What content is in tech LEF?

o Technology LEF (tech.lef): Defines the process technology rules and properties. It contains information common to the entire chip manufacturing process, independent of specific standard cells.

Content:

Layers: Defines all routing (metal), cut (via), masterslice (poly, diffusion), and other layers used in the technology. Includes name, type, direction preference, pitch, width, spacing rules (DRCs), resistance, capacitance per unit area/length, thickness, color (for multi-patterning).

Vias: Defines standard via types connecting different layers, including their cut patterns, enclosure rules, and resistance.

Which state (switching or not switching) consumes more power? Which VT leaks more (HVT vs LVT)?

oSwitching State: The switching state consumes significantly more power in CMOS circuits. This is called dynamic power and has two main components:

Switching Power: Charging and discharging load capacitances (Psw​=αCVdd2​f, where α is activity factor, C is load capacitance, Vdd is supply voltage, f is frequency).

Short-Circuit Power: For a brief moment during switching, both PMOS and NMOS transistors can be partially ON, creating a direct path from VDD to VSS.

How do you approach AOCV in your design? What kind of library do you need for AOCV?

Enable AOCV Mode: Set the appropriate variables/commands in the STA tool (e.g., PrimeTime, Tempus)

Specify AOCV Files: Ensure the tool points to the necessary AOCV library files (often provided as separate .aocv files or tables within the .lib).

Select Analysis Mode: Choose between ‘clock only’ or ‘clock and data’ modes. ‘Clock only’ applies AOCV derates just to clock paths for faster runtime, while ‘clock and data’ applies them to both for higher accuracy.

What is the difference between OCV, AOCV, and POCV? Why POCV?

Sources of Variation: The primary sources of variation that necessitate derates are:

·PVT (Process, Voltage, Temperature) Variations: These are inter-chip variations.

o Process: Variations in manufacturing (e.g., lithography wavelength, defects) can alter transistor parameters like oxide thickness, dopant levels, and physical dimensions (W/L), which in turn affect threshold voltage (Vt​) and current (I), and thus cell delay. Dies at the center of a wafer are more accurate than those at the periphery.