General-Concepts Interview Questions

oTSV (Through-Silicon Via): A vertical electrical connection (via) that passes completely through a silicon wafer or die. Used in 3DIC or 2.5D Chips, allowing different dies to be stacked vertically and interconnected directly using TSV and bumps.

• Physical Definition (LEF): A TSV would be defined in a manner similar to a standard via but with unique properties:
• Layer Type defined as “TSV” so tool understands it is not normal cut layer.
• It would have specific landing and covering layers (top and bottom metals it connects to).
• Dimensions (diameter, pitch).
• TSV-to-TSV or other metal spacing rules

oMulti-Patterning Rules: Assigning diff masks to shapes based on adjacent mask, if it is odd cycle violation, loop violation.

• Via Rules:
• Via Stacking & Alignment: Very tight rules on stacking multiple vias and their alignment to metal layers above and below.
• Via Enclosure by Metal: Stricter metal enclosure around vias.
• Interconnect Rules:
• Minimum Metal Pitch: Extremely tight metal width and spacing rules.
• End-of-Line (EOL) Spacing: Specific, often larger, spacing required at the ends of metal lines.
• Complex Conditional Spacing: Spacing rules that change based on parallel run length, adjacent feature types, or layer.
• fixing-double-patterning-errors-at-20nm

VT Types: Lower Vt has less delay variation across corners compared to higher vt

Cell Types: delay buffers and complex cells has higher variation compared to normal buf/inverter.

Yes, it is possible and quite common to see negative setup and hold times specified in standard cell timing libraries (.lib).

There are internal delays along the clock path and data path within the cell, from the input pins to the internal latch.

Negative Setup: If the internal clock path delay is significantly longer than the internal data path delay plus the internal latch’s intrinsic setup time, the data pin (D) can actually change after the active clock edge at the clock pin (CK) and still be captured correctly.

o Static Power: Power consumed when the circuit is powered ON but not actively switching. It’s primarily due to leakage currents flowing through transistors that are supposed to be OFF.

Main Components: Subthreshold leakage, gate leakage, junction leakage.

Factors: Increases significantly with lower threshold voltages (Vt) and at smaller technology nodes. Also increases with temperature.

Dynamic Power: Power consumed during the switching of logic states (when signals transition between ‘0’ and ‘1’).

oCMOS stands for Complementary Metal-Oxide-Semiconductor. It’s the dominant technology for constructing integrated circuits.

oComplementary: It uses both NMOS (N-channel Metal-Oxide-Semiconductor) and PMOS (P-channel Metal-Oxide-Semiconductor) transistors, typically paired together.

oStructure:

o**NMOS:** Conducts current (electrons) when its gate voltage is high (logic '1').  Built on a P\-type substrate.

o**PMOS:** Conducts current (holes) when its gate voltage is low (logic '0'). Built on an N\-type substrate (or N\-well).

oBasic Inverter: The fundamental CMOS gate is the inverter. It consists of one PMOS transistor connecting the output to VDD (power supply) and one NMOS transistor connecting the output to VSS (ground).