General-Concepts Interview Questions

If “MyIP” is instantiated at top level netlist, but if no definition is found of MyIP, then it becomes unresolved reference.

my_module u1 (.clk(clk), .rst(rst)); // ‘my_module’ is not defined anywhere in netlist or not found definition through .lib as well.

Blackbox:

module my_module (input clk, input rst);

// No internal implementation here

Endmodule

In this case, my_module is blackbox, as it is defined but only ports, no internal logic defined.

oDo We Need DFM? - YES

• DFM (Design for Manufacturability): A set of design methodologies and practices aimed at creating layouts that are not only DRC-clean but are also robust against normal manufacturing process variations, leading to higher yield. DFM often deals with “preferred” or “recommended” configurations that are known to be more robust.
• How DFM is Introduced in the Tech File:
• Redundant via insertion – Double cut vias and via enclosers defined in tech lef
• Antenna rules defined in tech file.
• EM: tech lef/file can define basic current density rules.
• Min and max area of shape.
• design-for-manufacturability

The selection involves a trade-off between PnR runtime/effort and signoff accuracy/coverage.

Signoff: Aims for comprehensive coverage of all conditions the chip might experience. It typically includes:

Multiple PVT Corners: Extremes of Process (SS, FF, SF, FS), Voltage (min, max), and Temperature (min, max), plus typical (TT).

Multiple RC Corners: Worst/Best RC combinations (RCworst, RCbest, Cworst, Cbest, potentially crosstalk corners).

Multiple Modes: Functional modes, test modes (Scan Shift, Scan Capture, BIST), potentially low-power modes.

oEnable Post-CTS/Post-Route Optimization:

• Innovus: optDesign -postCTS (after CTS), optDesign -postRoute (after routing). These commands invoke timing-driven optimization engines.
• ICC2: clock_opt -stage cts_optimize (after CTS build), route_opt (performs routing and optimization iteratively).
• Specify Effort Levels: Increase the optimization effort.
• Innovus: setOptMode -effort high|extreme
• ICC2: Options within place_opt, clock_opt, route_opt to control effort (e.g., -effort high).
• SI-Aware Optimization: Ensure Signal Integrity (crosstalk) aware optimization is enabled if SI violations are contributing to timing issues.
• Innovus: setOptMode -crosstalkAware true
• ICC2: set_si_options -delta_delay true -glitch true; route_opt -xtalk_driven
• Role of “Useful Skew”:

Setup Violation Fixing:

oIn a low-power project with specific operating performance points (OPPs) like:

• “low_svs” (Low Standard Voltage Swing, likely a power-saving mode)
• “turbo” (a high-performance mode, likely at a higher voltage),

Setup Analysis:

low_svs Mode: Analyze setup at the slowest process corner (SS/SSG) combined with VddL and worst-case temperature (often high temp for CMOS). This is SSG_VddL_HighTemp_RCworst. This represents the slowest the logic will be in low power mode.

turbo Mode: Analyze setup at the slowest process corner (SS/SSG) combined with VddH and worst-case temperature. This is SSG_VddH_HighTemp_RCworst. This is the absolute performance bottleneck.

oThey are used when signal crosses asynchronous clock domains.

Sync Flop added between two flops operating on asynchronous clocks to avoid metastability.

The main responsibility of a synchronizer is to allow sufficient time such that any meta-sable output can settle down to a stable value in the destination clock domain.

Generally 2 stage synchronizer is sufficient to remove all likely meta-stability.

Sync flops operating on destination clock domain.