General-Concepts Interview Questions

The selection involves a trade-off between PnR runtime/effort and signoff accuracy/coverage.

Signoff: Aims for comprehensive coverage of all conditions the chip might experience. It typically includes:

Multiple PVT Corners: Extremes of Process (SS, FF, SF, FS), Voltage (min, max), and Temperature (min, max), plus typical (TT).

Multiple RC Corners: Worst/Best RC combinations (RCworst, RCbest, Cworst, Cbest, potentially crosstalk corners).

Multiple Modes: Functional modes, test modes (Scan Shift, Scan Capture, BIST), potentially low-power modes.

oEnable Post-CTS/Post-Route Optimization:

• Innovus: optDesign -postCTS (after CTS), optDesign -postRoute (after routing). These commands invoke timing-driven optimization engines.
• ICC2: clock_opt -stage cts_optimize (after CTS build), route_opt (performs routing and optimization iteratively).
• Specify Effort Levels: Increase the optimization effort.
• Innovus: setOptMode -effort high|extreme
• ICC2: Options within place_opt, clock_opt, route_opt to control effort (e.g., -effort high).
• SI-Aware Optimization: Ensure Signal Integrity (crosstalk) aware optimization is enabled if SI violations are contributing to timing issues.
• Innovus: setOptMode -crosstalkAware true
• ICC2: set_si_options -delta_delay true -glitch true; route_opt -xtalk_driven
• Role of “Useful Skew”:

Setup Violation Fixing:

oIn a low-power project with specific operating performance points (OPPs) like:

• “low_svs” (Low Standard Voltage Swing, likely a power-saving mode)
• “turbo” (a high-performance mode, likely at a higher voltage),

Setup Analysis:

low_svs Mode: Analyze setup at the slowest process corner (SS/SSG) combined with VddL and worst-case temperature (often high temp for CMOS). This is SSG_VddL_HighTemp_RCworst. This represents the slowest the logic will be in low power mode.

turbo Mode: Analyze setup at the slowest process corner (SS/SSG) combined with VddH and worst-case temperature. This is SSG_VddH_HighTemp_RCworst. This is the absolute performance bottleneck.

o Traditional Corners (Simplified View - often just called C corners initially): Used for short nets where resistance can be ignored or very less.

Cworst (Maximum Capacitance, Cmax): Models process variations that maximize interconnect capacitance (e.g., wider wires, thicker metal, smaller spacing, higher dielectric constant). Often assumes minimum resistance for these conditions (though not always explicitly linked). Used primarily for setup timing analysis (longest path delay).

Cbest (Minimum Capacitance, Cmin): Models process variations that minimize interconnect capacitance (e.g., narrower wires, thinner metal, larger spacing, lower dielectric constant). Often assumes maximum resistance. Used primarily for hold timing analysis (shortest path delay).

Yes, it is possible and quite common to see negative setup and hold times specified in standard cell timing libraries (.lib).

There are internal delays along the clock path and data path within the cell, from the input pins to the internal latch.

Negative Setup: If the internal clock path delay is significantly longer than the internal data path delay plus the internal latch’s intrinsic setup time, the data pin (D) can actually change after the active clock edge at the clock pin (CK) and still be captured correctly.

o Static Power: Power consumed when the circuit is powered ON but not actively switching. It’s primarily due to leakage currents flowing through transistors that are supposed to be OFF.

Main Components: Subthreshold leakage, gate leakage, junction leakage.

Factors: Increases significantly with lower threshold voltages (Vt) and at smaller technology nodes. Also increases with temperature.

Dynamic Power: Power consumed during the switching of logic states (when signals transition between ‘0’ and ‘1’).