Floorplan Interview Questions

oRouting Congestion: Macros create “pinch points” or areas of high congestion around the corners and between adjacent macros, making it difficult for the router to connect signals. And creates Routing Detours resulting in longer wire lengths, increased delay, and potentially new timing violations.

• Sub-optimal Standard Cell Placement: tool not able to optimize placement.
• Power Distribution Issues: If a macro is particularly power-hungry, placing it in the middle of the core can cause a significant local IR drop unless the power grid is specifically reinforced in that area.
• Clock Tree Synthesis (CTS) Challenges: Macros can obstruct clock tree routing, making it harder for CTS tools to build a balanced tree with low skew.

• Power Grid Integrity: Due to lower Vdd and higher current density, the power grid must be extremely robust. This means more metal layers allocated for power
• Pin Placement Complexity: Higher pin counts and tighter bump pitches make I/O pin placement challenging.
• Increased Pin Density & Access: Macros at 7nm often have extremely high pin densities. This requires wider channels, careful orientation and blockages.
• Complex DRCs:
• Timing Impact: Due to high wire resistance

o Placement blockage of type “Hard” means that placeDesign will not place any cells in this area. Use this blockage type to totally restrict standard cells from being placed here.

A placement blockage of type “Soft” means that placeDesign will not place any cells in this region. However, placement legalization, timing optimization, and clock tree synthesis (CTS) can place buffers/inverters in this area. This blockage type is often used to block channels between macros. It prevents the placer from placing standard cells in this area, thus avoiding congestion problems. However, optimization is allowed to insert buffers/inverters in these channels, which is useful when buffering long nets and can improve timing and routability.

Area and Utilization: within limit.

Macro Placement Legality: Ensure all macros are placed legally (not overlapping) and are aligned to the site grid.

Pin Placement: Check that all I/O pins are placed and that their locations are reasonable for top-level connectivity.

Early IR Drop Analysis: A static IR drop analysis is run on the power distribution network (PDN) to check for significant voltage drops. This helps validate that the power grid structure (straps, rails, and vias) is robust enough.

o Target Utilization at Start: The initial target core utilization for PnR typically ranges from 50% to 70%.

Lower utilization (e.g., 50-60%) provides more whitespace, making routing easier, reducing congestion, potentially improving timing (less detour), and offering more flexibility for CTS and ECOs. This is often preferred for high-performance designs or designs with known congestion challenges.

Higher utilization (e.g., 65-70%, sometimes even higher for specific blocks) aims to minimize die area (cost). However, it increases the risk of congestion, may make timing closure harder, and leaves less room for post-route optimizations and ECOs.