Floorplan Interview Questions

o Decap Cells (Decoupling Capacitors): These are essentially capacitors (often MOSCAPs) placed near switching logic.

Need: to supply instantaneous current demands during fast switching events, stabilizing the power supply voltage (VDD/VSS) and mitigating dynamic IR drop and voltage noise on the power grid

Filler Cells: These cells fill the empty spaces left in standard cell rows after placement and optimization. They typically only contain VDD/VSS connections and substrate/well contacts.

Need: Ensure N-well and substrate continuity for proper biasing. Provide continuous power rail connections along the rows. Required for manufacturability (uniform density for CMP - Chemical Mechanical Polishing).

If macros having pins in middle or side with no pins can be abutted if technology allows.

o Filler Replacement: Tools often place decaps in available whitespace within standard cell rows, replacing filler cells. This is the most common method.

Near High-Switching Logic: Targeted placement near blocks or cells known to have high switching activity (e.g., clock buffers, data path muxes, bus drivers).

Around Macros: Placing decap cells in the channel space surrounding memory macros or other large IP blocks.

Under Power Straps: Some flows allow placing decap cells directly underneath higher-level power grid straps.

o Minimize wire length between pins and the internal logic/macros they connect to.

Reduce routing congestion, especially near the block boundary.

Align pins logically with connected blocks at the next level of hierarchy.

Meet timing requirements for critical interface paths.

Ensure routability and avoid pin access issues.

Group related signals (e.g., buses) together logically.

• Understand Connectivity: Analyze which internal blocks/macros connect to which I/O pins (using flylines or schematics). Understand connectivity to external blocks at the top level.
• Consider Top-Level Context: If the block is part of a larger design, align pin locations with the corresponding connections on adjacent blocks or routing channels at the top level to minimize top-level routing detours.
• Tool Assistance: PnR tools provide features for pin placement:

Automatic placement based on connectivity (“snap pins” or similar).

o Gather Inputs:

Gate Count: Number of standard logic gates from synthesis (excluding memories/macros).

Memory/Macro Area: Total area required for all hard macros, RAMs, ROMs, IP blocks (obtained from their datasheets or abstracts).

IO Count: Number of Input/Output pads/bumps required.

Technology Information: Gate density (gates/mm²) for the target standard cell library, standard cell height, required IO pad dimensions/pitch.

Target Utilization: The desired percentage of the core area that will be occupied by standard cells and macros after placement.

oAnalyze Connectivity (Flylines) – all fanin, all_fanout.

• Use trace macro feature of Innovus.

Group by Hierarchy/Connectivity

Consider Data Flow:

Periphery Placement: Generally place macros around the edges of the core area, leaving the central area for standard cells. This simplifies power delivery to macros and avoids blocking standard cell placement/routing in the core center.

Pin Accessibility: Orient macros so their pins face towards the core logic they connect to, minimizing wire length and routing complexity.