Floorplan Interview Questions

o Decap Cells (Decoupling Capacitors): These are essentially capacitors (often MOSCAPs) placed near switching logic.

Need: to supply instantaneous current demands during fast switching events, stabilizing the power supply voltage (VDD/VSS) and mitigating dynamic IR drop and voltage noise on the power grid

Filler Cells: These cells fill the empty spaces left in standard cell rows after placement and optimization. They typically only contain VDD/VSS connections and substrate/well contacts.

Need: Ensure N-well and substrate continuity for proper biasing. Provide continuous power rail connections along the rows. Required for manufacturability (uniform density for CMP - Chemical Mechanical Polishing).

o Gather Inputs:

Gate Count: Number of standard logic gates from synthesis (excluding memories/macros).

Memory/Macro Area: Total area required for all hard macros, RAMs, ROMs, IP blocks (obtained from their datasheets or abstracts).

IO Count: Number of Input/Output pads/bumps required.

Technology Information: Gate density (gates/mm²) for the target standard cell library, standard cell height, required IO pad dimensions/pitch.

Target Utilization: The desired percentage of the core area that will be occupied by standard cells and macros after placement.

oAnalyze Connectivity (Flylines) – all fanin, all_fanout.

• Use trace macro feature of Innovus.

Group by Hierarchy/Connectivity

Consider Data Flow:

Periphery Placement: Generally place macros around the edges of the core area, leaving the central area for standard cells. This simplifies power delivery to macros and avoids blocking standard cell placement/routing in the core center.

Pin Accessibility: Orient macros so their pins face towards the core logic they connect to, minimizing wire length and routing complexity.

o Placement blockage of type “Hard” means that placeDesign will not place any cells in this area. Use this blockage type to totally restrict standard cells from being placed here.

A placement blockage of type “Soft” means that placeDesign will not place any cells in this region. However, placement legalization, timing optimization, and clock tree synthesis (CTS) can place buffers/inverters in this area. This blockage type is often used to block channels between macros. It prevents the placer from placing standard cells in this area, thus avoiding congestion problems. However, optimization is allowed to insert buffers/inverters in these channels, which is useful when buffering long nets and can improve timing and routability.

o Target Utilization at Start: The initial target core utilization for PnR typically ranges from 50% to 70%.

Lower utilization (e.g., 50-60%) provides more whitespace, making routing easier, reducing congestion, potentially improving timing (less detour), and offering more flexibility for CTS and ECOs. This is often preferred for high-performance designs or designs with known congestion challenges.

Higher utilization (e.g., 65-70%, sometimes even higher for specific blocks) aims to minimize die area (cost). However, it increases the risk of congestion, may make timing closure harder, and leaves less room for post-route optimizations and ECOs.