ECO Interview Questions

oIt requires careful analysis and is typically done for critical paths where there is no scope in data path.

• For setup:
• Early the launch clock or delay the capture clock so skew can be increased which helps in setup violation. With this you are reducing the skew in path before and after this path. So there should be setup margin in both adjacent paths and hold margin in same path.
• For Hold:
• Delay the launch clock or early the capture clock so skew can be reduced which helps in hold violations. Path should have setup margin. And path before and after this path should have hold margin as for them it will increase the skew.
• Analyze Clock Path:
• Trace the launch and capture clock paths for the violating timing path.
• Identify existing buffers/inverters on these clock paths, their drive strengths, and locations.
• Understand the common clock path and the diverging points.
• Make desired changes after diverging point, ex, upsize, downsize, add delay based on setup or hold fix.
• Apply ECO in PNR tool and run STA to verify fixes

Understanding the Interaction:

• IR Drop -> Setup Violation: Voltage drop (IR drop) at a cell reduces its effective supply voltage, making it slower. This increased cell delay can directly cause or worsen a setup violation.

• Setup Fix -> IR Drop: Some setup fixes, like upsizing cells or swapping to lower Vt, increase the current draw (both peak and average) of those cells. This can worsen IR drop in the local region if the power grid is already marginal.

o Functional ECOs generally take precedence over DFT ECOs if the bug impacts core functionality. For scan ECO, test coverage target need to be checked, if without scan ECO, test coverage is below required target, it is must and other options must be evaluated.

o After post route database has acceptable timing and drc numbers, we start ECO phase.

• If power recovery is reuired, start with power recovery where tool downsize or VT swap cells in timing paths with positive slack to save power.
• Then start fixing drv/setup/hold timing. Generate ECO file manually or from STA tool, on single session or DMSA environment. Apply ECO on post route database in PNR tool, save design and dump outputs and rerun timing, Physical verification like DRC, LVS, Antenna, etc. IR EM analysis can be done.
• Iterate ECO cycles till timing is clean. Once all ECOs are implemented and locally verified, run full signoff checks (STA, DRC, LVS, EM/IR) on the final ECOed database.
• ECO Flow: https://teamvlsi.com/2021/02/eco-flow-in-physical-design.html

oFunctional ECO: An Engineering Change Order implemented to fix a logical bug in the design’s functionality or to add/modify a feature. The change originates from an RTL modification.

• RTL code is modified to fix the bug or add the feature.
• The changed RTL is synthesized (often just the affected module).
• Synopsys Formality ECO, Cadence Conformal ECO compares the original synthesized netlist (the one in PnR) with the newly synthesized netlist from the changed RTL.
• The ECO tool identifies the logical differences and generates a set of gate-level changes (ECO patch – add/delete/modify gates and connections) needed to transform the PnR netlist to match the new functionality. This patch is often a sequence of tool commands (add_cell, remove_cell, connect_net, disconnect_net, etc.).

Implementation in PnR: The ECO patch (script) is applied to the PnR database, followed by incremental placement (legalization) and routing of the modified logic.

oA “cell cannot be legalized” error during an ECO (especially a hold ECO, which often involves adding buffers) means the PnR tool cannot find a valid, DRC-clean placement location for the newly added or modified cells that aligns with the site rows and doesn’t overlap with other cells.

High Cell Density/Congestion: There’s simply no physical space (empty sites) to place the new buffer without causing overlaps.

Filler cells not removed from the design.