CTS Interview Questions

oUsually, data path logic is high

• If gater is not cloned or not cloned efficiently, can create balancing issues and result in timing vios.
• If latency is not in control or net and high drive strength cells are don’t use can create difficulty in ckg timing closure.
• Usually, CKG path having negative skew resulting in difficulty in setup fixes. Negative skew because CTS try to balance skews between CKG fanout and FF before it.

oWhy Different Layers:

• Top Nets: These are the initial long branches of the clock tree. That distributes clock all over the block. They are placed on higher metal layers because these layers have thicker wires with lower resistance, which is critical for minimizing the overall tree latency.
• Trunk and Leaf Nets: As the tree branches out closer to the flops, it moves to intermediate and lower metal layers. These layers are better for shorter, high-density routing.
• Why Not Shield All Layers:
• Routing Resource Congestion: Shielding consumes routing resources. Adding a VSS/VDD shield next to every clock wire would make it impossible to route the rest of the design’s signals.
• Not all the clock net’s need shielding, Shielding is most effective on the long nets that are most susceptible to coupling. Leaf-level nets are shorter and may not show critical level of coupling.

oClock groups might be updated after CTS based on new tree topologies causing new violation.

• Physical Detours and Congestion: The newly inserted clock buffers and routing can create congestion, forcing data path signals to take longer routes (detours) around the clock tree structures, thereby increasing their delay.
• CTS might trigger ECO fixes or buffer legalization that shifts data path buffers or cells.
• Actual skew values achieved is more than expected and considered in uncertainty, causing mismatch.
• CTS fixes DRC. And move around cells can cause timing violation.
• Very tight CTS constraint can cause CTS to add more buf/inv creating congestion and shifting nonCTS cells.

oEnable Post-CTS/Post-Route Optimization:

• Innovus: optDesign -postCTS (after CTS), optDesign -postRoute (after routing). These commands invoke timing-driven optimization engines.
• ICC2: clock_opt -stage cts_optimize (after CTS build), route_opt (performs routing and optimization iteratively).
• Specify Effort Levels: Increase the optimization effort.
• Innovus: setOptMode -effort high|extreme
• ICC2: Options within place_opt, clock_opt, route_opt to control effort (e.g., -effort high).
• SI-Aware Optimization: Ensure Signal Integrity (crosstalk) aware optimization is enabled if SI violations are contributing to timing issues.
• Innovus: setOptMode -crosstalkAware true
• ICC2: set_si_options -delta_delay true -glitch true; route_opt -xtalk_driven
• Role of “Useful Skew”:

Setup Violation Fixing:

o The top-level SDC must correctly define the clocks reaching the input clock ports of the sub-blocks.

If a sub-block generates clocks that are used by other blocks or the top level, these generated clocks must also be properly defined (e.g., using create_generated_clock sourced from a sub-block’s output pin).

• Sub-Block Timing Model (.lib**) and Physical Abstract (LEF):**
• CTS Exceptions for Sub-Block Pins: