CTS Interview Questions

oTransition Time (Slew):

• Set a max_transition constraint. tool will automatically insert buffers as needed to ensure no segment of the clock tree exceeds this targeted trans limit.
• Skew:
• Set a target skew limit. tool will use this as a target for balancing.
• Clock mesh or multi tap CTS instead of a conventional tree, or building a well-balanced H-tree, can control skew.
• Using NDRs with wider wires reduces RC variation, which helps minimize skew.

oLibrary Characterization: The cell library (.lib file) specifies a maximum transition time for which the cell delays are accurately characterized. Exceeding this can lead to inaccurate timing analysis. Your max_transition value must be within this characterized range.

• Very tight transition target can cause more latency, unnecessary buf/inv insertion.
• Thumb Rule: A common practice is to set the clock transition target to be about 10-15% of the clock period as a starting point, then tighten or loosen it based on power and performance requirements.

o Meeting Skew Targets: Verify achieved skew (global and local/group) against specified targets using CTS reports (report_clock_timing).

Meeting Latency Targets: Check min/max insertion delays against requirements.

Meeting DRCs: Ensure no max_transition, max_capacitance, or max_fanout violations

Duty Cycle Preservation: Check for duty cycle distortion. Ensure minimum pulse width requirements are met.

Balanced Structure: Visually inspect the tree or use tool reports to check for reasonably balanced branches. Global skew gives idea on how overall CTS is balanced.

oDuring CTS:

• Optimize Skew Groups: Define logical skew groups for paths to ensure they are balanced together.
• Use Non-Default Rules (NDRs): Apply NDRs to critical clock paths to use wider wires and greater spacing, reducing delay and crosstalk susceptibility.
• Clock Buffer Selection: Ensure the tool is using a good mix of clock buffers and inverters with less variation.
• Set clock targets appropriately like, skew, latency, DRC.
• Post-CTS:
• Run Post-CTS Optimization: Use commands like clock_opt (ICC2) or ccopt_design (Innovus) which are specifically designed to fix timing violations after the clock tree is built.
• Useful Skew:
• Clock gate optimization.

• Correct SDC Definition: Correctly define the generated clock in the SDC file, specifying its source pin (master clock) and the division/multiplication logic.

• Automatic Tool Handling: The CTS tool reads the SDC and understands the relationship between the master clock and the generated clock.

• Balancing: When balancing, the tool traces the generated clock’s path back to its source on the master clock’s tree. It then balances the latency from the clock source all the way to the sinks of both the master and generated clocks, ensuring they are properly aligned according to their defined relationship.

o Correct SDC Definition: Correctly define the generated clock in the SDC file, specifying its source pin (master clock) and the division/multiplication logic

• Automatic Tool Handling: The CTS tool reads the SDC and understands the relationship between the master clock and the generated clock.
• Balancing: When balancing, the tool traces the generated clock’s path back to its source on the master clock’s tree. It then balances the latency from the clock source all the way to the sinks of both the master and generated clocks, ensuring they are properly aligned according to their defined relationship.
• Exception Handling: You can define generated clocks as part of a separate skew group or mark them as dont_touch if you want to exclude them from the primary clock tree build and handle them with a custom structure.