CTS Interview Questions

What is clock skew? What causes skew? How to balance skew?

o Clock Skew: The difference in arrival time of the clock at capture FF and launch FF.

Local Skew: Skew between two specific, related flops (e.g., launch and capture flop of a timing path).

Global Skew: The difference between the maximum and minimum clock latency across all sinks in a domain.

Causes of Skew:

Different Path Lengths: The physical distance (wire length) from the clock root to different sinks varies due to their placement locations.

Where should clock gaters be placed (near sink or source)?

oIf you place ICG near to source, dynamic power consumption will reduce. This is because most of the clock buffers are in fanout of clock gater. These clock buffers will not toggle when clock gating is enabled.

  • But placing ICG near to source increases the uncommon paths. These uncommon paths can behave differently, so during STA these need to be taken into account that extra uncertainty.
  • If you place ICG near to sink, most of the clock buffers are in common path. It is easy to met timing compared to scenario-1.
  • But at the same time dynamic power consumption is increased.
  • Remember, there is trade-off between power and timing.
  • Ideally, Integrated Clock Gating (ICG) cells should be placed physically close to the group of flip-flops (sinks) they are gating.

Improve CTS Balancing: CTS tools balance delay up to the inputs of the ICG cells. Placing the ICG close to the sinks means the final, unbuffered gated clock segment is short and contributes less variable delay, making overall skew balancing more predictable.

How do you instruct your tools to resolve post-clock violations? What role does “useful skew” play in these scenarios?

oEnable Post-CTS/Post-Route Optimization:

  • Innovus: optDesign -postCTS (after CTS), optDesign -postRoute (after routing). These commands invoke timing-driven optimization engines.
  • ICC2: clock_opt -stage cts_optimize (after CTS build), route_opt (performs routing and optimization iteratively).
  • Specify Effort Levels: Increase the optimization effort.
  • Innovus: setOptMode -effort high|extreme
  • ICC2: Options within place_opt, clock_opt, route_opt to control effort (e.g., -effort high).
  • SI-Aware Optimization: Ensure Signal Integrity (crosstalk) aware optimization is enabled if SI violations are contributing to timing issues.
  • Innovus: setOptMode -crosstalkAware true
  • ICC2: set_si_options -delta_delay true -glitch true; route_opt -xtalk_driven
  • Role of “Useful Skew”:

Setup Violation Fixing: